1. Field of the Invention
The invention relates generally to semiconductor processing. In particular, the invention relates to the method and apparatus for removing defects from a silicon wafer prior to device fabrication.
2. Background Art
The increased density of devices formed on advanced silicon integrated circuits has required raw silicon wafers to have a further reduced density of defects. Although silicon wafers are substantially monocrystalline, they may suffer from several types of surface and bulk defects.
A slip defect occurs when the silicon is not perfectly monocrystalline. Instead, boundaries may develop in the bulk silicon across which the silicon atoms do not perfectly line up. Slip is believed to arise from shear stress. If the slip is large, a silicon plane on one side of the boundary may gradually transition between multiple silicon planes on the other side. Such a large slip renders that part of the silicon wafer essentially useless for integrated circuits. There are various degree of slip, but nearly invariably slip propagates and worsens with additional thermal processing. Strain introduced by slip can cause substantial difficulties, such as accelerated dopant diffusion in the vicinity of the strained material, resulting in a non-uniform diffusion density, or concentration of impurities around the slip.
We believe that many occurrences of slip arise during high temperature processing steps in which the silicon wafer moves over a supporting surface of a wafer fixture, such as a boat or tower, primarily because of differential thermal expansion of the two materials. Slip seems to become a particular problem when minimum feature sizes are less than 0.18 μm, which is the approximate size for advanced processing at the current time.
Another type of defect produces what are called crystal originated pits (COPs), which are agglomerated vacancy defects occurring at the wafer surface. Crystalline silicon typically contains a significant number of atomic defects in the form of vacancies and interstitials. The vacancies tend to agglomerate into larger voids distributed throughout the silicon. Any such void exposed at the wafer surface appears as a pit. These voids and pits are generally formed in what is otherwise a uniform, monocrystalline wafer. COPs become a major problem at minimum feature sizes of 0.13 μm, the size being contemplated for the next generation of integrated circuits.
There are several conventional methods of reducing if not eliminating the occurrence of crystal originated pits. In one method, the wafer is cut from a Czochralski-grown or float-zone crystallized ingot, is rounded, and has flats or other orienting indicia cut into its periphery. For some applications such as solar cells, the silicon wafer may be polycrystalline. The wafer is often then polished on both sides although in the past polishing has been limited to one wide. At this stage, a large number of COPs are typically present. In one method to remove the COPs, the wafer is then annealed at high temperature, for example, 12 hours at 1250° C., in a hydrogen environment. The high temperature promotes diffusion of silicon interstitials into the pits, thus planarizing the surface and eliminating the pits. The hydrogen is beneficial in promoting the diffusion of interstitials throughout the silicon wafer. The mobilized interstitials fill the surface pits.
The high-temperature COP anneal has not however been completely successful. One problem is that the annealing temperature is not that far below the melting point of silicon, which is approximately 1414° C. The long, hot COP anneal is likely to cause the silicon wafer supported at a minimum number of points to sag. Even if the wafer returns to its planar shape upon cooling, stress is likely to be thereby introduced. Sag becomes even more of a problem as the transition progresses from 200 mm to 300 mm wafers.
Quartz boats and towers are inadequate for these high temperatures because they sag at these temperatures. As a result, silicon carbide boats or towers are typically used for high-temperature processing because silicon carbide remains strong at significantly higher temperatures. However, silicon carbide presents its own set of problems. It is likely to contain a significant concentration of heavy metals, which are also mobilized by the high-temperature hydrogen anneal and which are very deleterious to semiconductor devices into which the heavy metals may diffuse. Solutions are available to address these problems, but they are both expensive and not completely effective.
It is further been observed that a COP anneal or other high-temperature anneal using a silicon carbide tower, even of the best design, is likely to introduce slip at the locations at which the tower supports the wafer. We believe the slip arises due to the differential coefficients of thermal expansion between silicon and silicon carbide and due to the silicon carbide being harder than silicon.
For these reasons, it is desired to provide a method and apparatus for more effectively performing a high temperature anneal of a silicon wafer.